A 3D-IC Feasibility Study flow is tried by a group of interested companies[1]. The presented flow is illustrated in the above figure.

[1] H. Murata (Gem Design Tech), A. Ohta (Ansoft Japan), K. Maeda (ANSYS Japan), and K. Nogita (Kitakyushu Foundation for the Advancement of Industry Science and Technology, FAIS), "Thermal Aware 3D-IC Planning", Japan ANSYS Conference, I-5, Nov. 20, 2009. (in Japanese)

  This is the first presented flow for 3D-IC designs, based on commercial tools, in the best of our knowledge. In the flow, a design is carried out in the following three steps.

• Physical model is constructed by using GemPackage.
• DC analysis is carried out by using Ansoft SIwave.
• Thermal analysis is performed by using ANSYS Icepak.

  The model is visually observed using Google Earth from time to time. The steps are retried accordingly, although they are described in series in the following.

  GemPackage has been revised recently to cover 3D-IC issues. (See Advanced Packages page of the product information). Its database is reasonably extended to unify 3D-ICs with traditional packages. Using the tool, example data is created for the project as follows. Three chips are stacked and connected by TSVs and pattern routings in re-distribution layers (RDLs). Die sizes are commonly set to 10mmx10mm. The die thicknesses are set 100um, 100um, 200um, respectively for the top chip, middle chip, and bottom chip. The top chip has its IOs on the bottom surface only. Other two chips have TSVs for the through connections, and also have face-down IOs for bottomward connections. All the TSVs are assumed as 20um diameter column shape objects. The IOs (including TSVs) are placed on 200um pitch regular grid.

  The nets and routings are made as follows. The main power supply (power/ground net pair) is installed at the center of the chip with 7x7 TSVs and they are connected mainly by stacked TSVs. Two other sub power supplies are installed at the four corners of the chips. Other signals are created randomly and connected mainly in zigzag fashion using TSVs for vertical connections and RDLs for the horizontal connections. The two RDLs between the three chips are routed with 20um/20um line/space rules, whereas the two RDLs implemented on the bottom of the bottom chip are routed with 60um/60um rules. (Each layer can be assigned with an individual design rule in GemPackage). The bottom RDL contains ball pads on 600um pitch 15x15 BGA (ball grid array).

  Above described is denoted as the standard configuration. Other versions are derived to see the effect of the design choices to the electrical/thermal performance as follows. (See above figures). 'manytsv' is created by increasing the number of TSVs for the main power source from 7x7 to 11x11. Two versions of floorplans are created inside a chip, by turning the chip to a sub-design. A board data is created, and on which the standard 3D-IC and other two chips are placed and routed out in four routing layers, where two inner layers are mainly for power/ground planes.

  Two ANF files (Ansoft Nutral Files) are created by GemPackage, one for 3D-IC part and another for board level data. They are combined in Ansoft system to re-configure the entire system, as in the left figure. A static DC analysis is prepared as follows. Current sources are assumed as the external power sources. The leakage current of the transistors are assumed constant thus the chips are modeled as resistors in the power circuits. Material constants are set accordingly. Then, the DC analysis is run. As the result, current, voltage, and power distributions are obtained. The above left figure shows the power distribution result.

  It is observed, in the 3D-IC part, that the power consumption in the power routings is 0.15W in standard design, and 0.1W in the 'manytsv' design. The reason of the power reduction in 'manytsv' would be because the external power source is modeled as current source. That is, the increase in the number of TSVs made more current paths which reduces the equivalent resistance and improves IR drops thus reduces the power consumption.

  The model file of Icepak is directly created by GemPackage, thus opened by Icepak as existing data. (above left figure). In the model file, the TSV's are modeled as tall rectangular box shape objects (instead of round column objects) to simplify the meshing process. The RDL patterns are provided in Gerber files and imported in Icepak to consider their effect on thermal conductance. The above left figure shows the pattern data as well. The power consumption in the routings, calculated by SIwave, is imported as distributed heat source cells into Icepak, when needed, as in the above right four figures.

  The top (as well as middle and bottom) chip is assumed to have planar uniform 0.1W (0.1W, 0.3W, resp.) heat source at its surface. The boundary condition is set such that the heat can flow out at the bottom of the 3D-IC only. The material constants are set accordingly. Then, the thermal analysis is carried out for the standard case, and for 'manytsv' case. The result is obtained as follows.

  In the figure, it is observed that the 'manytsv' shows larger temperature drop at the center of the top chip. This effect can be explained by the increase of the thermal conductivity in Z-direction, which is brought not only directly by more TSVs but also indirectly by more micro-bump balls and RDL patterns those come with TSVs.