It often happens that the system to be studied consists of multiple design hierarchies. For example, chip/package/board are individual design hierarchies, but studied as whole for high-speed applications. Another example is Package-on-Packege (PoP), where parent package and child package must be considered at once for better IO assignment. When the system involves two or more design hierarchies, traditional design method focuses one by one independently. GemPackage supports "super-hierarchical design", which enables the transparent view of whole system.

  Above figure demonstrates the difference between the super-hierarchical design and the traditional hierarchical design. In the super-hierarchical design (above left figure), the child package exposes its contents in the parent package. Even when the design efforts are forcusing on either hierarchy, the whole system can be observed. In the traditional hierarchical design (above right figure), the child package is treated as a black box in the parent design. In the child package design, the parent package is simply out of sight.

  The super-hierarchical design has following benefits, especially useful in FS phase.

• IO net assignments and signal routs of important signals can be designed in whole system view point.
• When IO net is changed, the netlist in affected sub-hierarchies are automatically maintained. Hence, the consistency of the net information is preserved automatically for whole system.

  To communicate with traditional systems, GemPackage can break its super-hierarchical design to individual designs, as well as re-organize them into super-hierarchical design.

  In high speed systems, critical signals need detailed care in deciding their pin assignment, based on a bird view of the entire Chip-Package-Board (CPB) structure. The super-hierarchical design abilityof GemPackage can solve this problem efficiently. The above figure depicts an example view of GemPackage for a CPB project. The left figure shows the board level view, where you can observe routing adjustment that connects to the in-design package. Four couples of differential signals are highlighted. In the middle figure, the in-design package is enlarged with surrounding board level routings. In the right figure, chip level floorplan, with IP blocks, is shown with surrounding package level routing. As in the figure, other design hierarchies can be made always visible in GemPackage while optimizing net assignments and routings in specific design hierarchy.

  PoP is a type of hierarchical design, and traditional tools handle them by focusing one hierarchy at a time putting others black boxes. However, the overall structure provides a system function, whole design should be visible to optimize the interfaces. GemPackage provides super-hierarchical design functionality which enables observing designs beyond the design hierarchy even when specific hierarchy is focused. For example, when a bonding pad is selected on child package, the connected objects in parent package are also highlighted. (above figure).