In today's high speed chip designs, chip IO layout and their net assignment should be determined in the package view. To answer to that need, GemPackage has ability to design chip IOs during the package FS.

　Dies can be created in the tool, with specified number of IOs placed, as well as imported from a spreadsheet data. Staggering the diepads is possible in the tool. Random netlist creation function is implemented to generate 'reasonable' nets on dies, for the very early design stage, with considerations for power/ground pin densities, buss widths, etc. Semi-auto style netlist generation is also possible with specified signal/power/ground ratio (above figure, left). It is possible to swap pin nets, shift nets (above figure, right), copy/paste nets. These functions are implemented seamlessly with bonding design/interposer routing design functions to improve chip IO design during the package FS. Bonding wires, as well as interposer rats, can be swapped 'upwardly', i.e. chip IOs are interchanged so that crossings in bonding wires/substrate traces are eliminated. When net is changed on specific chip IO, the change automatically propagates to balls and other chips through routings. It is also possible to stop such propagation by lock the balls/chip IOs. By those functions, chip IOs can be optimized during the package FS. The consistency of the netlist v.s. physical connection is always maintained automatically. It is also possible to export the netlist to Microsoft Excel, make some change on it by your customer, and re-import it. GemPackage takes the netlist change, and remove minimal traces if needed to keep the consistency.