The BGA net optimization is one of the most fundamental function of package design. Above figure depicts the function of auto-assignment of BGA nets, considering the bonding pad locations. It is also possible to make assignment for selected partial set of bonding pads and balls. Further, manual adjustment functions are possible, such as copy-and-pasting the chip nets into BGA balls, swapping nets of two selected balls, locking the ball nets to prevent the net change, etc.

  In high-speed wide-band applications, multiple occurrence of high-speed macros are needed, and their signals are hoped to form physical groups in chip IOs and in package IOs. For such applications, designer can introduce groups in chip IOs and package IOs, and set up group-to-group net assignment constraints. Once set, the net assignment functions begin considering the constraints.

  The differential signals are heavily used in current high speed designs. GemPackage has an automatic constraint generation function that acknowledges the differential signals by their names, and force the pair of signals to be assigned in adjacent positions in IOs. Once set, the net assignment functions begin considering the constraints.

  The BGA net assignment must also consider routing paths. In GemPackage, the net assignment functions consider the current sketch to re-optimize the ball assignment, to satisfy the constraints and to minimize the rats crossings. Then, designer can re-optimize the ball assignment during the substrate routability study, which finally converges to the net assignment that simultaneously satisfies the constraints and substrate routability.

  Above description assumes the net assignment is optimized outwardly, i.e. changing the package IOs while chip nets are fixed. However, high-speed chips needs inward optimization as well, i.e. changing the net assignments on chip IOs while package IOs are fixed. GemPackage has almost same functionality for inward net assignment optimization as the outward functions described above.