The most time consuming work in the SiP FS (Feasibility Study) phase would be the interposer routability analysis, which is to study whether all the nets is possible to be routed in the intended interposer (with specific size, layers, design rules), as quickly as possible. The task is typically done by a PCB design specialist because the task is believed requires 'deep experience'. 　Why the task is so hard? The major reason is, we think, that the designer have to manipulate layout primitives (trace, vias, etc) by hand, while he has to think about the global routing in head. (See figure below).

  Such hand-head gap situation can only be handled if you are so trained that your hand moves automatically to achieve what you think. To alleviate the hand-head gap, GemPackage implements 'global routing' itself as distinct design objects, as 'bendable rats'. (See figure below).

  The rats are initially shown as straight lines as usual. (left figure). You can insert/move vias on them, as well as you can bend the rats. Busses are automatically recognized and they are bent at once. Buss signals automatically run parallel to each other keeping the proper spaces, intuitively showing how wide the buss would take space. As such, designer can make a rough sketch of the design quickly. (middle figure). Then, it is just one button task left to check the routability of your sketch. Furthermore, deformation to actual routing is also possible in one button. (right figure). This is what we call 'Sketch-and-Convert' methodology. Note that the bendable rats visualize the global routes, which makes what you operate matches to what you think about, and alleviates the hand-head gap.

  Various other functions are also available for interposer global design, such as flexible ball assignment, swapping many rats at once, etc. Buttons and menus are laid out in a convenient way, so that assembly designers and chip designers can analyze the routability by themselves in many designs. For difficult cases, PCB designer would be needed to follow, but good hints are usually left there, to draw a useful knowledge from his/her experience. In our academic experiment, the turn around time was reduced to 1/4 in avarage in industrial examples. Average response from our customers are 1/4 to 1/8.

  Manufacturing issues are also covered as far as it affects feasibility of the design. For example, plating tail designs, etchback designs, detailed DRC checks are supported in GemPackage. Then, PCB specialist can also use GemPackage for quicker global design and for improving the communication with chip designers. What it lacks with are mainly the tasks for improving yield, e.g. even spacing beyond the design rule, tear drop addition, pattern fills, etc. For such tasks, you can export GemPackage design data into major CAD system. (see Compatibility page for details).