Wide range of the package structures are supported from today's commodity types to the near future types. The list of supported package types includes: FBGA, PBGA, Wire-bonding, Flip-chip bonding, Stacked-SiP, Side-by-side SiP, Silicon-substrate SiP, CoC, PoP, PoP-module, Wafer-level CSP, Window-BGA, TSV-based 3D-IC, Embedded Substrate, High-end laminated substrate, and Dual Face Package.

  Both flip chip bonding and wire bonding are supported as bonding methods. The two methods can be used simultaneously in a design. Arbitrary number of chips can be involved in a design. Chips can be stacked, placed side-by-side, or boths. Chips can be placed on top of the substrate, as well as on the bottom of the substrate.

  Complex bonding wire designs can be handled; staggered chip IOs, staggered bonding pads, vertically stacked wires, multiple wire profiles, multiple bonding on single bonding pad, high-pin count desings, etc. In flip chip bonding, micro bump balls are explicitly represented, (not only the bonding pads on the substrate), in the database, and their sizes and shapes can be individually set for each die.

  The design must have a substrate. Supported substrates are; single layer substrate, two layer substrate, through-hole substrate, build-up substrate, laminated substrate, high end laminated substrate with build-up layers, etc. The routing layer of the substrate layer should be one or more. (no upper limit.) The list of available via ranges is implicitly set by design rule, thus the number of routing layers can be easily changed during the design. Each routing layer, as well as each dielectric layer, can be assigned with individual design rules. Above figure shows examples of through-hole 4 layer substrate (above), and 1-2-1 build-up substrate (below).

  Package-on-Package (PoP), Package-in-Package (PiP), Dual Face Package (DFP) tend to require multiple design hierarchy, which is well-supported by GemPackage. Above figure shows examples for PoP-based module (above) and DFP (below).

  WLCSP (Wafer Level CSP) requires RDL (Re-Distribution Layer) routing designs, additionaly developed on top (or bottom) of the chip. GemPackage can support the feasibility study for such products. Above left figure is an example study result of FC (Flip-Chip) based WLCSP, and above right figure shows an TSV-based WLCSP. The study result can be transfered to layout editors, via GDS-II file, for detailed design phase.

  The TSV (Through Silicon Via) technology is developing rapidly, and the design methodology for 3D-IC is demanded by advanced users. In GemPackage, TSV is physically modeled as 'through' IO that penetrates the chip, so that chips can be stacked vertically and connected by TSVs and RDLs. Therefore, GemPackage can be used for TSV-based 3D-IC, as a package-level and system-level tool. The above left figure shows an example where 3 chips are stacked and connected in zig zag way using TSVs and RDLs. In the above right figure, some TSVs are stacked and directly connected via micro-bump balls without using RDL routings.

  The semiconductor chips and SMD components can be placed between routing layers in GemPackage, as well as on top/bottom of the substrate. Therefore, GemPackage can be used for embedded substrate designs. Above figure shows a cut model of a design example where large chip is placed on top of the substrate, and smaller chip and 2 capacitor chips are embedded in core layer and bonded to the ceiling.

  The Window-BGA (WBGA) substrate, often used in memory packages, is well supported.