GemView can read 2-dimensional DXF file if layer names etc are properly arranged. Once the DXF file is read, 2D observation is possible inside GemView, and 3D observation is possible using Google Earth/Google SketchUp. Using this feature, you may come up with variety of usages. Three example ideas are presented in the following: Visualizing photocoupler 3D assembly structure, building lowcost tool chain for small size BGA packages, constructing Chip-Package-Board bird view from individual sub-designs.

  For analog/discrete semiconductor designs such as photocouplers, we believe Google Earth/Google SketchUp can help improving the work flow. (See Google Aided Chip Design page for detail). Then to support such efforts, following features are implemented in GemView.

• DXF file can be read in into GemView, and you can observe the design in 2D manner.
• 3D information can be added inside GemView.
• 3D model files can be exported from GemView to Google Earth/Google SketchUp.

  The 2D DXF file should be arranged in a way that GemView requires, in layer names, etc. A proparly arranged file example can be downloaded here. (disc.dxf,65KB) The rule is explained in GemView's manual¹, in detail.

  The 3D information that can be added is: chip thickness, substrate conductor layer thickness, dielectric layer thickness, solder ball dimension, micro bump ball dimensions (for flip-chip technology), bonding wire loop profile, etc. In bonding wire loop profile entry, GemView has a unique and convenient method, that is, you can read-in a photograph image of a bonding wire onto screen, and extract the curve by picking the image by mouse. Other ways are also possible.

  In 3D model exporting function, the design objects are stored in Google's database such that you can observe data in net oriented manner, as well as layer oriented manner. Further in GemView/Pro, bonding wire dimension can be shown in text data in the 3D model, e.g. closest bonding wire pair, longest wire length, room distance to the ceiling of the package mold, etc.

  Sample 3D model file for Google Earth can be downloaded here. (disc.kmz,4KB) After download, you can open the file by 'File/Open' menu in Google Earth. Select items in 'Place' column at the left hand side of its window to control which data items to show. Sample 3D model file for Google SketchUp can be downloaded here. (disc.rb,50KB) To read the file into SketchUp, invoke 'Window/Ruby console', and type in the command like:

load "C:/xxx/xxx/disc.rb"

  Set operation unit to 'inch' in Window/Model Info/Unit menu, since this data is organized for inch unit. Global apperance can be adjusted by Window/Style menu. Data items can be made visible or hidden via Window/Layer menu. After such setting, you can save the file into SKP format for next session for quicker read time. SKP file can be downloaded here. (disc.skp,308KB) To open SKP file, just use File/Open menu. Since SketchUp has data entry function also, you can import light-emitting chip and light-receiving chip into SketchUp, place them face to face, and measure the distance between bonding wire distance of the two chips, as in the above right figure. The resultant SKP file can be downloaded here. (photocoupler.skp,353KB)

  In research/experimental projects to study simple BGA pacakge, when the number of pins are small and routing structure is simple, the design time would not be very important. Rather, inexpensive methodology for discussions is requested. For such needs, a reasonable tooling would be: AutoCAD (or AutoCAD compatible CAD), GemView, and Google Earth/Google SketchUp.

• (step1) Physical design by AutoCAD
    Input chip, BGA substrate, bonding wire, substrate traces, using AutoCAD or AutoCAD compatible CAD, to produce DXF file.
• (step2) 2D observation/discussion using GemView
    You can observe the design net by net, wire height by wire height, substrate layer by substrate layer, etc in GemView.
• (step3) 3D observation using Google Earth / Google SketchUp
    Add 3D information and produce 3D model file using GemView. Then, you can conveniently observe your data in 3D using Google Earth / Google SketchUp.

  Above figure illustrates the flow for an 100-pin scale single chip BGA design. First, the physical design is done in DXF (left figure), then the data is transfered into GemView (middle figure), and finally transfered into Google SketchUp (right figure). The DXF used in above example can be downloaded here. (demo100.dxf,294KB)

  When the research/experimental phase is finished, the design time reduction will be more interested. At that phase, you can transit from AutoCAD based flow to GemPackage based flow smoothly, since GemView can output GPK file.

  Chip-Package-Board (CPB) and Package-on-Package (PoP) design has hierarchical structure which is made of two or more sub designs, then the viewer must have super-hierarchical functionality to provide a bird view of whole design. Not many systems have such ability, except for few exception e.g. GemView/GemPackage. Then in many practical design flow, it is still a common custome that sub designs are made individually, and combined together only inside the designer's brain. To alleviate this problem, GemView/Pro has functionality to configure CPB/PoP structure from the sub designs.

  Above figure shows a PoP design that dipicts this functionality. The left figure is the mother side sub design, middle figure is the child side sub design. These two designs are individual and may have different design rules. In the mother design, child design is represeted as a face-down component, where internal data is not accessible (as a chip). The right figure is the PoP design, constructed from the two sub designs, using GemView. The design is hierarchical (you can distinguish mother and child) but at the same time you can observe the design in a super hierarchical way. For example in the right figure, the internal routing data of mother and child are both visible at the same time, and notice that two bonding wires are selected in child design and the connected routing is highlighted in mother design. CPB and Module (PoP technology based module) can be constructed similarly, since the construction is possible in multi-level (mother/child/grand-child, etc). Once CPB/PoP design is constructed in GemView, GPK file can be output to resume feasibility study using GemPackage.