IC Package FS Tool For SiP/3D-IC
- To optimize net assignments in Chip-Package-Board global view
- As communication tool for chip/package/system designers
- For quick wire bonding design
- For quick substrate routability study
- To develop design flow for 3D-IC
IC Package Design Observation Tool
- For SiP user to examine data from SiP maker
- For 3D visualization of SiP designs
- As a lowcost tool for experimental package designs
TSV-based 3D-IC is moving to daily use
- TSV-based 3D-IC technology is rapidly moving from R&D stage to daily use
- Urgent issue is the FS flow involving quick 3D-modeling and EM/thermal analysis
- Such FS flow is presented using our tool
Using Google 3D Software For Chip Design
- Share target images with your customers
- Improve communication in design review
- Utilize 3D images for freshman
- You can improve your design process without heavy investment, by cleverly utilizing Google Earth / Google SketchUp.
- Our tool accelerates this move.