Semiconductor chips are becoming more and more complex to support the advancement of IT gears. The hardness of its design can be understood when thinking about tens of millions of transistors have to cooperate accordingly. Design hierarchies have been introduced to cope with the complexity. It inherently means a team work of designers to accomplish a design project. The most often cases today involves Mr. Chip, Mr. Package and Mr. Board working together to realize the heart of smartphones, etc. The three people actually represent three organizations, typically the divisions of a big company or the three professional service companies. To initiate the hierarchical design, they first define the interface between the hierarchies, and then individually start internal designs with recent DFM functions.

The biggest challenge in the hierarchical design process is in the first step, in defining the interface. It comes from the fact that the end user not only demands the transistor count, but also the signal speed. The high speed signal today is very fragile and sensitive to neighboring signals as well as own signal paths, thus shall not work correctly if the interface is not carefully determined. In defining the hierarchical interface, we now need a super-hierarchical view point.

In the rest of this article, we take an example design case to demonstrate the actual operations of designing hierarchical interfaces, in the super-hierarchical view point. The netlist management issue is also mentioned. GemPackage is used as the tool because of its super-hierarchical design capability and the ease of use to Mr. Chip, Mr. Package, and Mr. Board.