The 3D-IC here refers to a new type of IC-package, in which multiple dies are stacked and connected by TSVs (through-silicon-vias). Fundamental researches have been carried out for long time to realize such technology, because of the following good properties for high-end applications.

  • It can alleviate noise problems in mixed digital/analog SoC by separating the chips for digital/analog circuits.
  • It can minimize global wire length by utilizing TSVs, leading the reduction of wiring delay and IR drops.

  • Efforts have been paid also for cost reduction, for example, maximizing the wafer level handling in the production, maximizing the chip reuse based on 'platform' ideas in the design phase. Further, the recent cost increase in SoC makes 3D-IC being a practical choice. Then, 3D-IC is now gathering interests also from consumer type applications.

    The biggest concern of the designers is the thermal issue. High density implementation inherently causes thermal problems and 3D-IC is the extreme case. In the above left figure, four chips are stacked on a heatsink and connected by TSVs. Because of the poor thermal conductivity of the inter-die dielectric material, the top chip can be very hot, as in the right figure. A careful analysis is required in the design flow.

    Another big challenge is the EDA environment. Since each chip in 3D-IC is only a building block in the system, the locations and the net assignments of the chip IOs, including TSVs, must be optimized based on the package point of view, or further based on the board point of view. Traditional EDA environment cannot answer this needs. New EDA tools and proper flow are demanded to support 3D-IC design.